The invention relates to a method and system for providing 5V tolerant and back-drive circuit protection for a receiver input interface.
A typical integrated circuit device (IC) includes a core region 100, as illustrated in FIG. 1, and one or more functional elements or packages such as analog support/conversion circuitry 102. These are connected through an I/O interface 104 to pads 106 that allow the IC to be connected externally to other devices. The voltage levels vary for different portions of the IC, thus requiring special consideration to avoid exposing the various portions of the IC to excessive voltage levels. For instance, the core, I/O interface, and external circuitry to which the pads of the IC connect, typically will each support different voltages. Even within a typical CMOS core, voltages vary depending on the process used. For example, a 0.25 xcexcm process supports voltage levels of the order of 2.5 Vxc2x110%; a 0.18 xcexcm process supports voltage levels of the order of 1.8 Vxc2x110%; a 0. 15 xcexcm process supports voltage levels of the order of 1.5 Vxc2x110%, and a 0.13 xcexcm process supports voltage levels of the order of 1.2 Vxc2x110%. In contrast, the I/O interface needs to support 3.3 V typically. For ease of understanding the input voltage levels to the core have been identified as VDD and VSS while those for the I/O interface are indicated as VDDIO and VSSIO. Furthermore, the pads may be connected to circuitry operating in the 5 V range. For example, where the IC drives a PCI bus, it is important that the IC can withstand the higher voltages of the system that it is supporting. In order to supply the higher voltage, a dual gate process involving the use of thick gate oxides is commonly used in the case of sub-micron CMOS.
The issue of different voltage levels becomes particularly acute when trying to match one technology with another due to the different switching levels. TTL technology, for instance, typically operates in the 0 to 3V range (VDD=3V) and has a VIH of 2Vxc2x110% and a VIL of 0.8Vxc2x110%. Thus TTL will see a voltage of xe2x89xa72V as a high and xe2x89xa60.8V as a low. In contrast 3.3V LVCMOS logic will switch at different voltages depending on the process used. In the case of 0.18xcexc technology, VDD=1.8Vxc2x110%, VIH=0.65VDD=1.05 V (0.65 xc3x97lowest VDD=0.65xc3x971.62V), VW=0.35VDD=0.69V (0.35xc3x97highest VDD=0.35xc3x971.98). For 0.15xcexc technology, VDD=1.5Vxc2x110%, VIH=0.65 VDD, VIL=0.35 VDD.
In addition, the issue of 5V tolerant and back-drive protection has to be addressed. This may be illustrated by considering a simple circuit such as the one illustrated in FIG. 2, in which a receiver input comprises a PMOS transistor 200 and NMOS transistor 202 using 0.18xcexc technology, and connected to a pad 204 through an NMOS isolation transistor 206. The issue that arises is ensuring that PMOS 200 switches on correctly. With the gate voltage of transistor 206 at 3.3Vxc2x110%, the source voltage can be in the range of 2.5V to 3.1V, which, with 3V on the source of transistor 200, is not high enough to ensure that transistor 200 switches off.
Clearly, any solution addressing compatibility issues should ideally also be able to deal with stress mode conditions (5V tolerant mode and back-drive mode).
An IC may typically be operated in one of three modes: (a) Normal mode, in which the core is powered up and drives the pads; (b) 5V tolerant mode, which is a stress mode in which the pads are raised to about 5.5 V, while the core and I/O interface are powered up (VDD and VDDIO are high); (c) Back-drive mode, which is a stress mode in which the pads are raised to about 5.5 V, while the core and I/O interface are powered down (VDD and VDDIO are low). Thus back-drive refers to the 5.5 V tolerant interface when there are no power supplies asserted. This condition becomes particularly important in the case of sub-micron CMOS, dual gate process technology in which the oxide breakdown and drain-sourcejunction breakdown is about 3.8 V. Back-drive I/Os have to tolerate 5.5 V at the pads with and without power supplies asserted (commonly referred to as 5V tolerant level due to the 5Vxc2x110% tolerance). However, under stress mode, sub-micron dual gate devices tend to experience problems such as oxide breakdown, drain-source junction breakdown, current flow to VDDIO, and well charging due to the parasitic internal diode structure of CMOS devices.
In order to avoid gate oxide breakdown the voltage drop from drain to gate must not exceed 3.8 V. Similarly, to avoid junction breakdown, the voltage drop from drain to source must not exceed 3.8 V. Furthermore, it is necessary to isolate the receiver input circuitry from the pad under these stress modes.
The present invention seeks to provide a method and circuitry for protecting a receiver circuit under stress mode conditions and of ensuring proper switching of transistors implemented using different technologies and processes.
The present invention provides an input clamp circuit for providing stress mode protection of I/O receivers. Furthermore, the present invention provides a technique for enhancing the tolerance of a receiver input interface during 5V tolerant and back-drive mode, while allowing a LVTTL logic threshold and interface.
According to the invention there is provided circuitry to limit the potential difference across the CMOS transistors to avoid oxide breakdown and drain-sourcejunction breakdown. In particular the invention provides for a bias circuit supplied by a high external voltage, such as the pad voltage, to charge up the floating wells and floating nodes in order to limit the static DC bias potential below the maximum stress level of the CMOS process. Preferably the resultant circuit comprising the receiver input with its bias circuit is not only 5 V tolerant, but is also back-drive tolerant. Typically the worst case DC current used by this clamp circuit is less than 5 xcexcA.
The invention provides for a pass gate between the pad and the receiver input interface circuitry to isolate the receiver input circuitry from the pad voltage during stress mode. The pass gate typically includes a PMOS transistor connected in parallel with an NMOS transistor. The PMOS transistor is typically switched off during stress mode while the NMOS transistor provides a reduced voltage to the receiver input. Preferably the gate of the NMOS transistor is charged to a voltage NG1 of approximately 3 V or VDDIO.
According to the invention, there is provided a method of protecting a receiver input during back-drive mode, comprising charging up the floating nodes during back-drive mode, to the level of the supply voltage to limit the voltage across the drain-source junction and across the gate-active node junction of all transistors to below the junction breakdown and gate oxide breakdown voltage levels.
Further, according to the invention, there is provided a method of protecting a receiver input during stress mode, comprising providing a full pass gate between the receiver input and a pad, and, during 5V tolerant and back-drive modes, charging up the gate of the PMOS transistor of the pass gate to shut it off and clamp the voltage to the receiver input at the supply voltage level.
Further, according to the invention, there is provided a method of ensuring proper functioning of the I/O receiver during normal mode, and stress mode in which the pad is exposed to a high voltage, while providing a LVTTL interface, comprising providing a pass gate with a NMOS and a PMOS transistor in parallel, between the pad and the receiver input, and selectively charging the gate of the PMOS transistor to the pad voltage during stress mode. The charging may be performed by means of a charging circuit connected to the pad.
Still further, according to the invention, there is provided a method of protecting an receiver input during stress mode, comprising providing a NMOS transistor between a high voltage pad and the receiver input to limit the voltage to the receiver input under stress mode, providing a PMOS transistor in parallel with the NMOS transistor, and controlling the PMOS to switch on during normal mode and switch off during stress mode. The method preferably includes clamping input voltage to the receiver input to a voltage that avoids gate oxide and junction breakdown. The clamping may be achieved by providing a clamping circuit that includes a current mirror between the receiver input and ground.